在高速多层PCB中,当信号从顶层传输到内部某层时,用通孔连接就会产生多余的导通孔短柱,多余短柱会引起反射、附加电容和电感,从而导致阻抗不连续、损耗等信号完整性问题。采用盲、埋孔虽可避免短柱,但成本较高,研究短柱对过孔信号完整性的影响有助于平衡成本与性能。本研究通过实验研究了短柱对单端、差分过孔阻抗的影响,并进一步研究了短柱对单端过孔信号损耗、谐振频率的影响。试验表明:过孔阻抗随短柱长度增加而下降;对于单端过孔,短柱长度每增加0.10mm,过孔阻抗下降(0.4-0.9)Ω;对于差分过孔,短柱长度每增加0.10mm,过孔阻抗下降(0.6-1.1)Ω。通过s参数曲线发现,短柱越长,单端过孔信号损耗越大,谐振频率越低。
In high-speed multilayer PCB, when signal moves from a top layer to an internal stripline structure, an excess via-hole stub is created. Unused portion causes reflection, capacitance and inductance, which result in impedance discontinuities and attenuation, and hence deterioration of signal integrity (SI). This study of via-hole stub allows the designers to decide tradeoff between cost (using blind or buried vias) and performance. By the experiments, it founded that impedance of vias decreased with the increasing of stub length. For single-ended vias, the impedance of vias decreased by 0.4-0.9 ohm when the length of stub increased by every 0.10 mm. For differential vias, the impedance of vias decreased by 0.6-1.1 ohm when the length of stub increased by every 0.10 mm. In addition, the longer the excess stub results in larger insertion loss, and leads to a lower resonant frequency.